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data sheet ics843001cgi-23 revision a october 4, 2011 1 ?2011 integrated device technology, inc. femtoclock ? crystal/lvcmos-to- lvpecl/ lvcmos frequency synthesizer ics843001i-23 general description the ics843001i-23 is a highly versatile, low phase noise lvpecl/lvcmos synthesizer which can generate low jitter reference clocks for a variety of communication applications. the dual crystal interface allows the synthesizer to support up to three communication standards in a given application (i.e. sonet with a 19.44mhz crystal, 1gb/10gb ethe rnet and fibre channel using a 25mhz crystal). the rms phase jitt er performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as oc48 so net, gbe/10gb ethernet and san applications. the ics843001i-23 is packaged in a small 24-pin tssop, e-pad package. features ? one 3.3vdifferential lvpecl output pair and one lvcmos/lvttl single-ended reference clock output ? selectable crystal oscillator interface or lvcmos/lvttl single-ended input ? crystal and clk range: 19.44mhz ? 27mhz ? able to generate gbe/10gbe/12gbe, fibre channel (1gb/4gb/10gb), pci-e and sata from a 25mhz crystal ? vco range: 1.12ghz ? 1.275ghz ? supports the following applications: sonet, ethernet, fibre channel, serial ata, and hdtv ? rms phase jitter @ 622.08mhz (12khz - 20mhz): 0.9ps (typical), 3.3v ? supply modes v cc /v cco 3.3v/3.3v 3.3v/2.5v 2.5v/2.5v ? -40c to 85c ambient operating temperature ? available in both standard (rohs 5) and lead-free (rohs 6) package pin assignment 11 10 01 00 00 01 10 11 phase detector vco 000 44 001 45 010 48 011 50 100 51 111 64 (default) n 000 2 001 4 010 5 011 6 100 8 (default) 101 10 110 12 111 16 m 3 3 osc osc q nq ref_out n2:n0 m2:m0 sel0 sel1 xtal_in0 xtal_out0 xtal_in1 xtal_out1 clk mr oe_ref pulldown pulldown pullup pulldown pulldown pulldown 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 v cco_lvcmos n0 n1 n2 v cco_lvpecl q nq v ee v cca v cc xtal_out1 xtal_in1 ref_out v ee m2 oe_ref m0 m1 mr sel1 sel0 clk xtal_in0 xtal_out0 ics843001i-23 24-lead tssop, e-pad 4.4mm x 7.8mm x 0.925mm package body g package top view block diagram
ics843001cgi-23 revision a october 4, 2011 2 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1v cco_lvcmos power output supply pin for ref_clk output. 2, 3 n0, n1 input pulldown output divider select pins. lvcmos/l vttl interface levels. see table 3c. 4 n2 input pullup 5v cco_lvpecl power output supply pin for lvpecl output. 6, 7 q, nq output differential outpu t pair. lvpecl in terface levels. 8, 23 v ee power negative supply pins. 9v cca power analog supply pin. 10 v cc power core supply pin. 11, 12 xtal_out1, xtal_in1 input parallel resonant crystal interface. xtal_out1 is the output, xtal_in1 is the input. 13, 14 xtal_out0, xtal_in0 input parallel resonant crystal interface. xtal_out0 is the output, xtal_in0 is the input. 15 clk input pulldown single-ended clock input. lvcmos/lvttl interface levels. 16, 17 sel0, sel1 input pulldown input mux select pins . lvcmos/lvttl interface levels. see table 3d. 18 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true output q to go low and the inverted output nq to go high. when logic low, the internal di viders and the outputs are enabled. lvcmos/lvttl interface levels. 19, 20, 21 m0, m1, m2 input pullup feedback divider select pins. lvcmos/lvttl interface levels. see table 3b. 22 oe_ref input pulldown reference clock output enable. default low. see table 3e. lvcmos/lvttl interface levels. 24 ref_out output reference clock output . lvcmos/lvttl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? r out output impedance ref_out v cco = 3.3v 21 ? v cco = 2.5v 25 ?
ics843001cgi-23 revision a october 4, 2011 3 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer function tables table 3a. common configuration table table 3b. programmable m feedback divider function table input frequency (mhz) m feedback divider value vco frequency (mhz) n output divider value output frequency (mhz) application 27 44 1188 16 74.25 hdtv 24.75 48 1188 16 74.25 hdtv 19.44 64 1244.16 8 155.52 sonet 19.44 64 1244.16 2 622.08 sonet 19.44 64 1244.16 4 311.04 sonet 25 50 1250 10 125 gige 25 50 1250 8 156.25 10 gige 25 50 1250 5 250 gige 25 50 1250 4 312.5 xgmii 25 50 1250 2 625 10 gige 25 45 1125 6 187.5 12 gige 25 48 1200 12 100 pci express 25 48 1200 8 150 sata 25 48 1200 16 75 sata 25 51 1275 12 106.25 fibre channel 25 51 1275 8 159.375 10 gig fibre channel 25 51 1275 6 212.5 4 gig fibre channel inputs m feedback divider value input frequency (mhz) m2 m1 m0 minimum maximum 0 0 0 44 25.5 27 0 0 1 45 24.9 27 0 1 0 48 23.3 26.56 0 1 1 50 22.4 25.5 1 0 0 51 22.0 25 1 0 1 64 (default) 19.44 19.92
ics843001cgi-23 revision a october 4, 2011 4 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer table 3c. programmable n output divider function table table 3d. select mode function table table 3e. oe_ref output function table inputs n divider value n2 n1 n0 000 2 001 4 010 5 011 6 1 0 0 8 (default) 101 10 110 12 111 16 inputs reference input pll mode sel1 sel0 0 0 xtal0 active (default) 01 xtal1 active 10 clk active 1 1 clk bypass input output oe_ref ref_out 0 high-impedance (default) 1 active
ics843001cgi-23 revision a october 4, 2011 5 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v cc = v cco_lvcmos = v cco_lvpecl = 3.3v 5%, v ee = 0v, t a = -40c to 85c table 4b. power supply dc characteristics, v cc = 3.3v 5%, v cco_lvcmos = v cco_lvpecl = 2.5v 5%, v ee = 0v, t a = -40c to 85c item rating supply voltage, v cc 4.6v inputs, v i xtal_in other input 0v to v cc -0.5v to v cc + 0.5v outputs, i o (lvpecl) continuous current surge current outputs, v o (lvcmos) 50ma 100ma -0.5v to v cco_lvcmos + 0.5v package thermal impedance, ja 32.1 c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.11 3.3 v cc v v cco_lvpecl, v cco_lvcmos output supply voltage 3.135 3.3 3.465 v i ee power supply current 140 ma i cca analog supply current outputs unterminated 11 ma symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage v cc ? 0.11 3.3 v cc v v cco_lvpecl, v cco_lvcmos output supply voltage 2.375 2.5 2.625 v i ee power supply current 139 ma i cca analog supply current outputs unterminated 11 ma
ics843001cgi-23 revision a october 4, 2011 6 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer table 4c. power supply dc characteristics, v cc = v cco_lvcmos = v cco_lvpecl = 2.5v 5%, v ee = 0v, t a = -40c to 85c table 4d. lvcmos/lvttl dc characteristics, t a = -40c to 85c . table 4e. lvpecl dc characteristics, v cc = v cco_lvpecl = 3.3v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco_lvpecl ? 2v. symbol parameter test conditio ns minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage v cc ? 0.10 2.5 v cc v v cco_pecl, v cco_cmos output supply voltage 2.375 2.5 2.625 v i ee power supply current 133 ma i cca analog supply current outputs unterminated 10 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage v cc = 3.3v 2 v cc + 0.3 v v cc = 2.5v 1.7 v cc + 0.3 v v il input low voltage v cc = 3.3v -0.3 0.8 v v cc = 2.5v -0.3 0.7 v i ih input high current clk, oe_ref, mr, n0, n1 sel0, sel1 v cc = v in = 3.465v or 2.625v 150 a n2, m[2:0] v cc = v in = 3.465v or 2.625v 5a i il input low current clk, oe_ref, mr, n0, n1 sel0, sel1 v cc = 3.465v or 2.625v, v in = 0v -5 a n2, m[2:0] v cc = 3.465v or 2.625v, v in = 0v -150 a v oh output high voltage ref_out v cco_lvcmos = 3.465v, i oh = -12ma 2.6 v v cco_lvcmos = 2.625v, i oh = -12ma 1.8 v v ol output low voltage ref_out v cco_lvcmos = 3.465v or 2.625v, i ol = 12ma 0.5 v symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cco_lvpecl ? 1.4 v cco_lvpecl ? 0.9 v v ol output low voltage; note 1 v cco_lvpecl ? 2.0 v cco_lvpecl ? 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v
ics843001cgi-23 revision a october 4, 2011 7 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer table 4f. lvpecl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v cco_lvpecl = 2.5v 5%, v ee = 0v, t a = -40c to 85c note 1: outputs terminated with 50 ? to v cco_lvpecl ? 2v. table 5. crystal characteristics note: characterized using an 18pf parallel resonant crystal. ac electrical characteristics table 6a. ac characteristics, v cc = v cco_lvcmos = v cco_lvpecl = 3.3v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the v cc /2 of the input to v cco_lvcmos /2 of the output. note 2: phase jitter measured using a 19.44mhz quartz crystal. note 3: ref_out output duty cycle characterized with clk input duty cycle between 48% and 52%. symbol parameter test conditio ns minimum typical maximum units v oh output high voltage; note 1 v cco_lvpecl ? 1.4 v cco_lvpecl ? 0.9 v v ol output low voltage; note 1 v cco_lvpecl ? 2.0 v cco_lvpecl ? 1.5 v v swing peak-to-peak output voltage swing 0.4 1.0 v parameter test conditions mi nimum typical maximum units mode of oscillation fundamental frequency 19.44 27 mhz equivalent series resistance (esr) 50 ? shunt capacitance 7pf symbol parameter test conditio ns minimum typical maximum units f out output frequency q, nq 70 637.5 mhz ref_out 19.44 27 mhz t pd propagation delay; note 1 clk to ref_out 2.2 2.7 ns t jit(?) rms phase jitter, (random); note 2 622.08mhz, (12khz ? 20mhz) 0.97 ps f vco pll vco lock range 1.12 1.275 ghz t r / t f output rise/fall time q, nq 20% to 80% 200 700 ps ref_out, note 3 20% to 80% 250 650 ps odc output duty cycle q, nq 46 54 % ref_out; note 3 using clock input 48 52 % t lock pll lock time 60 ms
ics843001cgi-23 revision a october 4, 2011 8 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer table 6b. ac characteristics, v cc = 3.3v 5%, v cco_lvcmos = v cco_lvpecl = 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the v cc /2 of the input to v cco_lvcmos /2 of the output. note 2: phase jitter measured using a 19.44mhz quartz crystal. note 3: ref_out output duty cycle characterized with clk input duty cycle between 48% and 52%. table 6c. ac characteristics, v cc = v cco_lvcmos = v cco_lvpecl = 2.5v 5%, v ee = 0v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the v cc /2 of the input to v cco_lvcmos /2 of the output. note 2: phase jitter measured using a 19.44mhz quartz crystal. note 3: ref_out output duty cycle characterized with clk input duty cycle between 48% and 52%. symbol parameter test conditio ns minimum typical maximum units f out output frequency q, nq 70 637.5 mhz ref_out 19.44 27 mhz t pd propagation delay; note 1 clk to ref_out 2.3 2.9 ns t jit(?) rms phase jitter, (random); note 2 622.08mhz, (12khz ? 20mhz) 1ps f vco pll vco lock range 1.12 1.275 ghz t r / t f output rise/fall time q, nq 20% to 80% 200 700 ps ref_out 20% to 80% 350 750 ps odc output duty cycle q, nq 46 54 % ref_out; note 3 using clock input 48 52 % t lock pll lock time 60 ms symbol parameter test conditio ns minimum typical maximum units f out output frequency q, nq 70 637.5 mhz ref_out 19.44 27 mhz t pd propagation delay; note 1 clk to ref_out 2.3 2.9 ns t jit(?) rms phase jitter, (random); note 2 622.08mhz, (12khz ? 20mhz) 1.1 ps f vco pll vco lock range 1.12 1.275 ghz t r / t f output rise/fall time q, nq 20% to 80% 200 700 ps ref_out 20% to 80% 350 750 ps odc output duty cycle q, nq 46 54 % ref_out; note 3 using clock input 48 52 % t lock pll lock time 60 ms
ics843001cgi-23 revision a october 4, 2011 9 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer typical phase noise at 622.08mhz . 622.08mhz rms phase jitter (random) 12khz to 20mhz = 0.97ps (typical) noise power dbc hz offset frequency (hz)
ics843001cgi-23 revision a october 4, 2011 10 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer parameter measureme nt information 3.3v lvpecl output load ac test circuit 2.5v lvpecl output load ac test circuit 3.3 core/2.5v lvpecl output load ac test circuit 3.3v lvcmos output load ac test circuit 2.5v lvcmos output load ac test circuit 3.3v core/2.5v lvcmos output load ac test circuit scope qx nqx v ee v cc, 2v -1.3v 0.165v v cco_lvpecl 2v v cca scope qx nqx v ee v cc, v cca v cco_lvpecl 2v -0.5v0.125v 2v scope qx nqx v ee v cc v cca v cco_lvpecl 2.8v0.04v -0.5v0.125v 2v 2.8v0.04v scope qx v ee 1.65v5% -1.65v5% v cca v cc, v cco_lvcmos 1.65v5% scope qx v ee v cc, v cca v cco_lvcmos 1.25v5% -1.25v5% 1.25v5% scope qx v ee -1.25v5% v cca v cco_lvpecl v cc 2.05v5% 1.25v5% 2.05v5%
ics843001cgi-23 revision a october 4, 2011 11 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer parameter measurement in formation, continued rms phase jitter lvpecl output duty cycle/pulse width/period lvpecl output rise/fall time lvcmos output duty cycle/pulse width/period lvcmos output rise/fall time offset frequency f 1 f 2 phase noise plot rms jitter = area under curve defined by the offset frequency markers noise power q nq t pw t period t pw t period odc = x 100% 20% 80% 80% 20% t r t f v swing q nq ref_out t period t pw t period odc = x 100% v cco_cmos 2 t pw 20% 80% 80% 20% t r t f ref_out
ics843001cgi-23 revision a october 4, 2011 12 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer applications information recommendations for unused input and output pins inputs: crystal inputs for applications not requiring the use of the crystal oscillator input, both xtal_in and xtal_out can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from xtal_in to ground. clk input for applications not requiring the use of the clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the clk input to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvpecl outputs the unused lvpecl output pair c an be left floating. we recommend that there is no trace attached. both sides of the differential output pair should either be left floating or terminated. lvcmos output all unused lvcmos output can be left floating. we recommend that there is no trace attached.
ics843001cgi-23 revision a october 4, 2011 13 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer overdriving the xtal interface the xtal_in input can accept a single-ended lvcmos signal through an ac coupling capacitor. a general interface diagram is shown in figure 1a. the xtal_out pin can be left floating. the maximum amplitude of the input signal should not exceed 2v and the input edge rate can be as slow as 10ns. this configuration requires that the output impedanc e of the driver (ro) plus the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? applications, r1 and r2 can be 100 ? . this can also be accomplished by removing r1 and making r2 50 ? . by overdriving the crystal oscillator, the device will be functional, but note, the device performance is guaranteed by using a quartz crystal. figure 1a. general diagram for lvcmos driver to xtal input interface figure 1b. general diagram for lvpecl driver to xtal input interface r2 100 r1 100 rs 43 ro ~ 7 ohm driv er_lvcmos zo = 50 ohm c1 0.1uf 3.3v 3.3v cry stal input interf ace xta l _ i n xta l _ o u t cry stal input interf ace xtal_in xtal_out r3 50 c1 0.1uf r2 50 r1 50 zo = 50 ohm lvpecl zo = 50 ohm vcc=3.3v
ics843001cgi-23 revision a october 4, 2011 14 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. the differential outputs are lo w impedance follower outputs that generate ecl/lvpecl compatible out puts. therefore, terminating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to drive 50 ? transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 2a and 2b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. figure 2a. 3.3v lvpecl output termination figure 2b. 3.3v lvpecl output termination 3.3v v cc - 2v r1 50 ? r2 50 ? rtt z o = 50 ? z o = 50 ? + _ rtt = * z o 1 ((v oh + v ol ) / (v cc ? 2)) ? 2 3.3v lvpecl input r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? lvpecl input 3.3v 3.3v + _
ics843001cgi-23 revision a october 4, 2011 15 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer termination for 2.5v lvpecl outputs figure 3a and figure 3b show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? to v cco ? 2v. for v cco = 2.5v, the v cco ? 2v is very close to ground level. the r3 in figure 3b can be eliminated and the termination is shown in figure 3c. figure 3a. 2.5v lvpecl driver termination example figure 3c. 2.5v lvpecl driver termination example figure 3b. 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
ics843001cgi-23 revision a october 4, 2011 16 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer schematic layout figure 6 (next page) shows an example of ics843001i-23 application schematic. in this example, the device is operated v cc = v cco_lvcmos = v cco_lvpecl = 3.3v. the 18pf parallel resonant 17.5-29.54mhz crystal is used. the load capacitance c1 = 22pf and c2 = 22pf are recommended for frequency accuracy. depending on the parasitic of the printed circui t board layout, these values might require a slight adjustment to optimize the frequency accuracy. crystals with other load capacitance specifications can be used. this will require adjusting c1 and c2. for this device, the crystal load capacitors are required for proper operation. as with any high speed analog circuitry, the power supply pins are vulnerable to random noise. to achieve optimum jitter performance, power supply isolation is requir ed. the ics843001i-23 provides separate power supplies to isolate any high switching noise from coupling into the internal pll. in order to achieve the best possible filtering, it is recommended that the placement of the filter componen ts be on the device side of the pcb as close to the power pins as possible. if space is limited, the 0.1uf capacitor in each power pi n filter should be placed on the device side. the other components can be on the opposite side of the pcb. power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. the filter performance is designed for wide range of noise frequency. this low-pass filter starts to attenuate noise at approximately 10khz. if a specific frequency noise component with high amplitude interference is known, such as switching power supplies frequencies, it is recommended that component values be adjusted and if required, additional filtering be added. additionally general design practice for power plane voltage stability suggests adding bulk capacitances in the general area of all devices. the schematic example focuses on functional connections and is not configuration specific. refer to the pin description and functional tables in the datasheet to ensure the logic control inputs are properly set.
ics843001cgi-23 revision a october 4, 2011 17 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer figure 6. ics843001i-23 layout example rd2 1k tl3 zo = 50 ohm c10 0.1uf (u1:1) logi c contr ol input exa mpl es v cc= 3. 3v m2 m0 ru2 not install se l 0 vc c ref_o ut c13 0. 1 u f vcco q 3.3v se l 1 zo = 50 o hm x2 17.5mhz - 29.54mhz q s et logi c input t o '0' 3.3v c11 10uf m urata, blm18bb221sn1 fb1 1 2 c8 10uf to logic input pins r3 133 r7 50 vdd vcca v cco_l v pecl= 3 .3 v zo = 50 ohm r1 33 c7 0.1uf c2 22pf xta l_ o u t0 v cco_l v cmos= 3. 3 v r2 133 ro ~ 7 ohm q1 driv er_lvcmo s ru1 1k + - c5 22 p f 3.3v vc c r4 10 s et logi c inpu t t o '1' /q lv cmos (u1:10) xtal _ i n 1 xtal_ i n 0 c12 0.1uf n0 c3 22pf c4 10u 1 8 p f c1 22pf m urata, blm18bb221sn1 fb2 1 2 vc c clk c6 0.1u r9 43 u1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 vcco_lvcmos n0 n1 n2 vcco_lvpecl q nq vee vcca vcc xta l _ o u t1 xta l _ in 1 xtal _ o u t0 xta l_i n 0 clk sel0 sel1 mr m0 m1 m2 oe_ref ve e ref_out xta l_ o u t1 zo = 50 o hm vcc vcco c9 0.1uf vcc + - 1 8 p f rd1 not install q nq opti ona l lvp ecl y- termi nati on r5 82.5 r10 50 z o = 50 ohm oe _re f m1 tl2 zo = 50 ohm /q vcco r6 82.5 to logic input pins (u1:5) n1 n2 r8 50 mr x1 17.5mhz - 29.54mh z
ics843001cgi-23 revision a october 4, 2011 18 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 7. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requiremen ts. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, refer to the application note on the surface mount assembly of amkor?s thermally/electrically enhance leadframe base package, amkor technology. figure 7. assembly for exposed pad thermal rel ease path - side view (drawing not to scale) ground plane land pattern solder thermal via exposed heat slug (ground pad) pin pin pad solder pin pin pad solder
ics843001cgi-23 revision a october 4, 2011 19 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer power considerations this section provides information on power dissipati on and junction temperature for the ics843001i-23. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics843001i-23 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. power (core) max = v cc_max * i ee_max = 3.465v * 140ma = 485.1mw power (outputs) max = 30mw/loaded output pair lvcmos output power dissipation output impedance r out power dissipation due to loading 50 ? to v ddo /2 output current i out = v ddo_max / [2 * (50 ? + r out )] = 3.465v / [2 * (50 ? + 21 ? )] = 24.4ma power dissipation on the r out per lvcmos output power (r out ) = r out * (i out ) 2 = 21 ? * (24.4ma) 2 = 12.5mw per output total power dissipation total power = power (core) + power (lvpecl output) + power (r out ) = 485.1mw + 30mw + 12.5mw = 527.6mw 2. junction temperature. junction temperature, tj, is the temperat ure at the junction of the bond wire and bond pad, and directly affects the reliabilit y of the device. the maximum recommended junction temperature is 125c. limiting the in ternal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 32.1c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.528w * 32.1c/w = 102c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 7. thermal resitance ja for 24 lead tssop, e-pad forced convection ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 32.1c/w 25.5c/w 24.0c/w
ics843001cgi-23 revision a october 4, 2011 20 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer 3. calculations and equations. the purpose of this section is to calculate the power dissipation fo r the lvpecl output pair. lvpecl output driver circuit and termination are shown in figure 7. figure 8. lvpecl driver circuit and termination t o calculate worst case power dissipation into the load, use the following equations which assume a 50 ? load, and a termination voltage of v cco ? 2v. for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max ? v oh_max ) = 0.9v for logic low, v out = v ol_max = v coo_max ? 1.7v (v cco_max ? v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v oh_max ) = [(2v ? (v cco_max ? v oh_max ))/r l ] * (v cco_max ? v oh_max ) = [(2v ? 0.9v)/50 ? ] * 0.9v = 19.8mw pd_l = [(v ol_max ? (v cco_max ? 2v))/r l ] * (v cco_max ? v ol_max ) = [(2v ? (v cco_max ? v ol_max ))/r l ] * (v cco_max ? v ol_max ) = [(2v ? 1.7v)/50 ? ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw v out v cco v cco - 2v q1 rl 50
ics843001cgi-23 revision a october 4, 2011 21 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer reliability information table 8. ja vs. air flow table for a 24 lead tssop, e-pad transistor count the transistor count for ics843001i-23 is: 4165 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 32.1c/w 25.5c/w 24.0c/w
ics843001cgi-23 revision a october 4, 2011 22 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer package outline and package dimensions package outline - g suffix for 24 lead tssop, e-pad table 9. package dimensions reference document: jedec publication 95, mo-153 all dimensions in millimeters symbol minimum maximum n 24 a 1.10 a1 0.05 0.15 a2 0.85 0.95 b 0.19 0.30 b1 0.19 0.25 c 0.09 0.20 c1 0.09 0.16 d 7.70 7.90 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.50 0.70 p 5.0 5.5 p1 3.0 3.2 0 8 aaa 0.076 bbb 0.10
ics843001cgi-23 revision a october 4, 2011 23 ?2011 integrated device technology, inc. ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer ordering information table 10. ordering information note: parts that are ordered with an "lf" suffix to the part number are the pb-free configuration and are rohs compliant. part/order number marking package shipping packaging temperature 843001cgi-23 ics843001ci23 24 lead tssop, e-pad tube -40c to 85c 843001cgi-23t ics843001ci23 24 lead tssop, e-pad 2500 tape & reel -40c to 85c 843001cgi-23lf ics43001ci23l ?lead-free? 24 lead tssop, e-pad tube -40c to 85c 843001CGI-23LFT ics43001ci23l ?lead-free? 24 lead tssop, e-pad 2500 tape & reel -40c to 85c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this produc t is intended for use in normal commercial and industrial applications. any other applications, su ch as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ics843001i-23 data sheet femtoclock ? crystal/lvcmos-to-lvpecl/lv cmos frequency synthesizer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own ri sk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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